Pinned Loading
-
Neural_Network_SystemVerilog_RTL
Neural_Network_SystemVerilog_RTL PublicImplementing a Neural Network Using SystemVerilog
-
Pipelined-RISC-V-Processor
Pipelined-RISC-V-Processor PublicThis projects constructs a simple version of a processor sufficient to implement most of RISC-V32I instructions
Verilog 1
-
stm32-wakemath-system
stm32-wakemath-system PublicEmbedded sleep-inactivity alarm using PIR motion sensing and STM32, requiring a math-problem challenge on an LCD/keypad to dismiss the buzzer.
C
-
logic-sim
logic-sim PublicA C++ event-driven digital logic simulator for educational and prototyping purposes. Simulates combinational and sequential circuits using time-ordered events, with a focus on clarity, correctness,…
C++
-
ahb-lite-systemverilog
ahb-lite-systemverilog PublicSystemVerilog implementation of an AMBA AHB-Lite bus, featuring a master, multiple slaves, and a comprehensive verification environment.
SystemVerilog
-
stm32l4xx-drivers
stm32l4xx-drivers PublicBare-metal, register-level drivers for STM32L432KC (Cortex-M4). GPIO, SPI, I2C, and UART implemented from the reference manual without HAL/LL dependencies.
C
If the problem persists, check the GitHub status page or contact support.